In Wong et al. U.S. Pat. No. 4,912,342, describe a programmable logic device (PLD) having a logic array block, providing a plurality of product term signals which are a logic function (AND) of the interconnected word lines, and a macrocell block receiving the product term signals for logically combining, storing, feeding back or outputting at least some of those product term signals. The macrocell block includes a flip-flop structure with a data input D receiving a signal that is a combination (OR/NOR) of several product term signals, an output Q and a clock input receiving an applied clock signal CLK, according to which the flip-flop structure will operate in either a combinatorial, asynchronous or synchronous mode. The applied clock signal CLK is provided by an OR gate that logically combines a first signal LABCLK and a product term signal ACLK. For combinatorial operation, flip-flop preset and reset signals P and C are simultaneously active (low) and the product term signal ACLK is programmed to be always 1, so that the applied clock signal CLK on the flip-flop's clock input is a constant logic signal 1. For asynchronous operation, the first signal LABCLK is programmed to be always 0, so that the applied clock signal CLK on the flip-flop's clock input is the product term signal ACLK, a function of the present states of word line variables in the logic array block. For synchronous operation, the product term signal ACLK is programmed to be always 0, so that the applied signal CLK on the flip-flop's clock input is an external clock signal EXT(SYNC)CLK provided on the LABCLK line by an input pad of the device. In this manner, the clocking of the flip-flop is programmable to select either combinatorial, asynchronous or synchronous mode operation of that flip-flop.
Certain non-programmable configurations for synchronizing clock signals and data signals for flip-flops and other storage elements are known. For example, in Pribyl U.S. Pat. No. 4,933,571, describes a circuit in which a data signal D is input into a flip-flop through a transfer gate controlled by a clock signal CLK. Data is thereby synchronized with the clock, preventing metastable conditions. In Alvarez, Jr. U.S. Pat. No. 4,011,465, describes a circuit in which a latch is driven by a data-modulated clock signal. The data-modulated clock signal is provided by an AND gate that logically combines an asynchronous data signal S.sub.IN with a clock signal .phi..sub.1. In Chunk et al. U.S. Pat. No. 4,740,721 and 4,841,174, describe a programmable logic array (PLA) and a circuit that may be implemented in a PLA which uses a clock signal CK and its complement CK to synchronize the dynamic logic operations of the logic gates in the PLA. Both the NAND and NOR planes of the PLA feed into latches. The clock signal not only controls the latches, but also logically combines with the terms of the planes of logic gates.
With reference to FIGS. 12-15, clock circuits of the prior art used for providing a clock signal CLK to a storage element, such as a flip-flop, are shown. In FIG. 12, a line 101 connected directly to an external contact or pin 102 of an integrated circuit device supplies an external clock signal EXT CLK as the clock signal CLK to be used by a storage element. This scheme has been used, for example, in Atmel Corporation's 22V10 programmable logic device. In FIG. 13, a line 103 conducts a product term signal P.T. provided by a logic circuit portion of the integrated circuit to a storage element to be used as its clock signal CLK. The product term signal P.T., and thus the clock signal CLK, will vary according to the inputs received by the logic circuit portion of the integrated circuit, causing an asynchronous operation of storage element. This scheme is used, for example, in Atmel Corporation's V750 and V2500 programmable logic devices. In FIG. 14, one conductive line 104 is connected to an external contact of an integrated circuit to receive an external clock signal EXTCLK from outside of the device. Another conductive line 106 receives a product term from a logic circuit portion of the integrated circuit that varies as a function of inputs to the logic circuit. A multiplexer 107 receives both signals on its inputs, namely conductive lines 104 and 106, and selects one of them to be connected to and transmitted over an output 108. The output 108 carries the selected signal as a clock signal CLK to a storage element. This circuit, which allows programmable synchronous or asynchronous operation of a storage element, is used, for example, in Altera Corporation's EP5xxx series of devices. In FIG. 15, another clock circuit also uses a multiplexer 109 to select one of two signals, an external clock signal EXTCLK from an external contact and an internally generated logic term S.O.P. from a logic circuit, as the clock signal CLK provided to a storage element of the integrated circuit. However, unlike the circuit in FIG. 14, this circuit uses a sum-of-products signal S.O.P. as the logic term instead of a product term P.T. The sum-of-products signal S.O.P. is generated by combining two or more product term signals P.T.#1 and P.T.#2 from an AND array of the logic circuit in an OR gate 11O. The resulting output is the sum-of-products signal S.O.P. that could be selected by the multiplexer 109. This circuit is used, for example, in Intel Corporation's SAC312 device.
As clock speeds employed for integrated circuits increase, it is desirable that chip performance, measured by parameters such as time from clock to output t.sub.CO, increase accordingly, so that logic generation can keep up with the faster clock. It is also desirable that integrated circuits be sufficiently flexible that storage elements in the circuits, such as flip-flops, are operable in either a synchronous or asynchronous mode, as selected by the user. For this reason, clock circuits for providing clock signals to such storage elements have been made programmable, as in FIGS. 14 and 15. However, such flexibility is a potential source of delay, such that the storage elements must wait for the generation of the clock logic after signals are provided at the contacts or pins of the device.
A more efficient clock circuit providing programmable synchronous versus asynchronous clocking of integrated circuit storage elements is sought.